Mechanical and chemical-mechanical planarizing processes (collectively "CMP") are used in the manufacturing of microelectronic devices for forming a flat surface on semiconductor wafers, field emission displays (FEDs) and many other types of microelectronic substrate assemblies. FIG. 1 schematically illustrates a planarizing machine 10 with a platen 20, a carrier assembly 30, a polishing pad 40, and a planarizing fluid 44 on the polishing pad 40. The planarizing machine 10 may also have an under-pad 25 attached to an upper surface 22 of the platen 20 for supporting the polishing pad 40. In many planarizing machines, a drive assembly 26 rotates (arrow A) and/or reciprocates (arrow B) the platen 20 to move the polishing pad 40 during planarization.
The carrier assembly 30 controls and protects a substrate 12 during planarization. The carrier assembly 30 typically has a substrate holder 32 with a pad 34 that holds the substrate 12 via suction, and a drive assembly 36 of the carrier assembly 30 typically rotates and/or translates the substrate holder 32 (arrows C and D, respectively). The substrate holder 32, however, may be a weighted, free-floating disk (not shown) that slides over the polishing pad 40.
The combination of the polishing pad 40 and the planarizing fluid 44 generally define a planarizing medium that mechanically and/or chemically-mechanically removes material from the surface of the substrate 12. The polishing pad 40 may be a conventional polishing pad composed of a polymeric material (e.g., polyurethane) without abrasive particles, or it may be an abrasive polishing pad with abrasive particles fixedly bonded to a suspension material. In a typical application, the planarizing fluid 44 may be a CMP slurry with abrasive particles and chemicals for use with a conventional nonabrasive polishing pad. In other applications, the planarizing fluid 44 may be a chemical solution without abrasive particles for use with an abrasive polishing pad.
To planarize the substrate 12 with the planarizing machine 10, the carrier assembly 30 presses the substrate 12 against a planarizing surface 42 of the polishing pad 40 in the presence of the planarizing fluid 44. The platen 20 and/or the substrate holder 32 then move relative to one another to translate the substrate 12 across the planarizing surface 42. As a result, the abrasive particles and/or the chemicals in the planarizing medium remove material from the surface of the substrate 12.
CMP processing is particularly useful in fabricating FEDs, which are one type of flat panel display in use or proposed for use in computers, television sets, camcorder viewfinders, and a variety of other applications. FEDs have a baseplate with a generally planar emitter substrate juxtaposed to a faceplate. FIG. 2 illustrates a portion of a conventional FED baseplate 120 with a glass substrate 122, an emitter layer 130, and a number of emitters 132 formed on the emitter layer 130. An insulator layer 140 made from a dielectric material is disposed on the emitter layer 130, and an extraction grid 150 made from polysilicon or a metal is disposed on the insulator layer 140. A number of cavities 142 extend through the insulator layer 140, and a number of holes 152 extend through the extraction grid 150. The cavities 142 and the holes 152 are aligned with the emitters 132 to open the emitters 132 to the faceplate (not shown).
Referring to FIGS. 2 and 3, the emitters 132 are grouped into discrete emitter sets 133 in which the bases of the emitters 132 in each set are commonly connected. As shown in FIG. 3, for example, the emitter sets 133 are configured into rows (e.g., R.sub.1 -R.sub.3) in which the individual emitter sets 133 in each row are commonly connected by a high-speed interconnect 170. Additionally, each emitter set 133 is proximate to a grid structure superjacent to the emitters that is configured into columns (e.g., C.sub.1 -C.sub.2) in which the individual grid structures are commonly connected in each column by another high-speed interconnect 160. The interconnects 160 are generally formed on top of the extraction grid 150. It will be appreciated that the column and row assignments were chosen for illustrative purposes.
In operation, a specific emitter set is selectively activated by producing a voltage differential between the extraction grid and the specific emitter set. A voltage differential may be selectively established between the extraction grid and a specific emitter set through corresponding drive circuitry that generates row and column signals to intersect at the location of the specific emitter set. Referring to FIG. 3, for example, a row signal along row R.sub.2 of the extraction grid 150 and a column signal along a column C.sub.1 of emitter sets 133 activates the emitter set at the intersection of row R.sub.2 and column C.sub.1. The voltage differential between the extraction grid and the selectively activated emitter sets produces localized electric fields that extract electrons from the emitters in the activated emitter sets.
The display screen of the faceplate (not shown) is coated with a substantially transparent conductive material to form an anode, and the anode is coated with a cathodoluminescent layer. The anode, which is typically biased to approximately 1.0-5.0 kV, draws the extracted electrons across a vacuum gap (not shown) between the extraction grid and the cathodoluminescent layer of material. As the electrons strike the cathodoluminescent layer, light emits from the impact site and travels through the anode and the glass panel of the display screen. The emitted light from each of the areas becomes all or part of a picture element.
One manufacturing concern with FEDs is that the layers of materials from which the interconnects and/or the extraction grid are formed are subject to cracking or de-laminating during CMP processing. In a typical process for fabricating the baseplate 120 shown in FIG. 2, a number of conformal layers are initially deposited over the emitters 132, and then the substrate assembly is planarized. For example, a conformal dielectric layer is initially deposited over the emitter layer 130 and the emitters 132 to provide material for the insulator layer 140. A conformal polysilicon layer is then deposited on the insulator layer 140 to provide material for the extraction grid 150, and a conformal metal layer is deposited over the grid layer to provide material for the interconnects 160. After all of the conformal layers are deposited, the baseplate sub-assembly is planarized by CMP processing to form a planar surface at an elevation just above the tips of the emitters 132. CMP processing, however, applies sheer forces to the substrate that often cause the metal interconnect layer to crack or de-laminate. Moreover, if the metal interconnect layer delaminates, it may also pull up a polysilicon extraction grid layer or even the silicon dioxide insulator layer because metals generally from very strong bonds with polysilicon. Thus, CMP processing may severely damage or even destroy microelectronic substrate assemblies for FED baseplates.
Another manufacturing concern is that there is a significant drive for developing large FEDs that can be used in computers, televisions and other large scale applications. The de-lamination of the metal interconnect layer during CMP processing, however, is particularly problematic for large FED applications because the surface area of larger substrate assemblies exacerbates the effects of the shear focus between the substrate assemblies and the polishing pads. Thus, CMP processing of FED baseplates is currently impeding progress in cost-effectively manufacturing large FEDs for consumer applications.